The present invention generally relates to the configuration of programmable logic devices, and more particularly to interfaces for configuring programmable logic devices.
In the past, configuring a programmable logic device (PLD) such as a field programmable gate array (FPGA) was relatively simple. The configuration data in the form of a configuration bitstream was stored in a some form of serial, non-volatile memory. The bitstream was then loaded into the FPGA with minimal hardware and software support. This approach continues to the present. However, the vast increase in the number of gates and the increased functionality of PLDs has made the simple configuration method very time consuming.
New configuration interfaces, for example, the SelectMap interface for the Xilinx Virtex(trademark) FPGA, are made to exploit new configuration capabilities of FPGAs and to reduce the time required to configure a device with a configuration bitstream. For example, the SelectMap interface supports partial reconfiguration, readback, partial readback and control functions such as reset. The SelectMap interface includes an eight-bit parallel port that significantly increases the configuration bandwidth over prior PLDs. Further details on the configuration of Xilinx FPGAs can be found on pages 3-14 to 3-23 of The Programmable Logic Databook 1999, which is available from Xilinx, Inc., and which pages are incorporated herein by reference.
Despite the new features and reduced configuration times, designers are often reluctant to use a new interface in view of the time required to learn the new interface and tight development schedules. For example, the SelectMap configuration/readback features require more complex hardware interfaces and additional software to make use of the features, compared to previous configuration interfaces. Thus, designers sometimes continue to use the old interface in order to save development time.
An interface arrangement and method that address the aforementioned problems, as well as other related problems, are therefore desirable.
An adaptable configuration interface for a programmable logic device (PLD) is provided in various embodiments of the invention. A PLD includes a plurality of configuration pins and circuitry implementing read and write protocols for reading data from and writing configuration data to the PLD. An interface register that is external to the PLD is connected to the configuration pins of the PLD, and a processor is coupled to the register. The flip-flops of the register correspond to the configuration pins of the PLD, whereby programs executing on the processor can interact with the PLD during the configuration and readback of data. A first set of routines, each executable on the processor, are configured to read and write values from and to the register. A second set of routines, each executable on the processor, provide an application programming interface for configuration and reading back data from the PLD via the first set of routines. The layered structure of the software components of the interface arrangement supports incrementally adapting the PLD interface arrangement from more software control to a combination of less software and more hardware control. Thus, as a design nears completion, the configuration performance can be enhanced by implementing more of the interface arrangement in hardware. It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims, which follow.